SRAM cells provide a high-density and fast on-chip storage solution that may be implemented in many of today's integrated circuits (ICs). A conventional six transistor (6T) SRAM cell is a bi-stable latching circuit that relies on the relative strength of each of the transistors in the cell for storing a bit of data. FIG. 1 illustrates a standard 6T SRAM cell 100, in accordance with the prior art. It will be appreciated that the SRAM cell illustrated in FIG. 1 is only one type of SRAM cell and that other types (e.g., 4T, 8T, 10T) exist as well. As shown in FIG. 1, the SRAM cell 100 includes six MOSFET (Metal Oxide Semiconductor Field Effect Transistors). The SRAM cell 100 has four main MOSFETs, two p-type MOSFETs (PMOS) (i.e., 111 and 112) and two n-type MOSFETs (NMOS) (i.e., 113 and 114), that form two cross-coupled inverters (i.e., the input of the first inverter is connected to the output of the second inverter and the input of the second inverter is connected to the output of the first inverter). The first inverter comprises PMOS 111 and NMOS 113 having the drain terminals coupled to a common node and the gate terminals coupled to another common node. The second inverter comprises PMOS 112 and NMOS 114 having the drain terminals coupled to a common node and the gate terminals coupled to another common node. Then the drain terminals of each inverter are coupled to the gate terminals of the other inverter. The source terminals of PMOS 111 and PMOS 112 are coupled to a supply voltage (VDD) and the source terminals of NMOS 113 and NMOS 114 are coupled to a ground potential. The cross-coupled inverters are stable in one of two states that represent a logic-high and a logic-low.
The SRAM cell 100 may be accessed using the word line (WL) signal to turn on the access MOSFETS (i.e., NMOS 115 and NMOS 116). In order to read the SRAM cell 100, the bit lines (i.e., the BL signal and the complement of the BL signal) are pre-charged to a logic-high value and then the WL signal is asserted on the word line. The cross-coupled inverters charge or drain each of the bit lines, which are then compared by a sensing amplifier (not shown) to determine the state of the SRAM cell 100. In order to write the SRAM cell 100, the value to be written to the SRAM cell 100 is applied to the bit lines and then the WL signal is asserted on the word line. The bit line drivers are much stronger than the MOSFETs of the cross-coupled inverters so the signals on the bit lines override the current state of the cross-coupled inverters to latch in the new value of the SRAM cell 100.
One of skill in the art would recognize that the proper operation of the SRAM cell 100 relies on the relative strength of the components of the device as well as the drivers of the signals applied to the bit lines and word line. For example, as already mentioned, the drivers for the bit lines must be sized to overcome the feedback from the cross-coupled inverters. In addition, during a read operation, the voltage disturbance on the internal nodes resulting from the voltage divider comprising the access MOSFETs and a corresponding MOSFET in the cross-coupled inverters should be small enough not to disturb the state of the cell. However, in sub-micron technologies, individual transistors may exhibit large variations in operating characteristics due to manufacturing conditions. In other words, the relative strengths of devices on the IC may be skewed, which may cause the SRAM cell 100 to not operate properly. Furthermore, it is becoming increasingly more difficult to design critical circuits such as sense-amplifiers in deeply scaled CMOS fabrication processes, where device sizes are digitized and longer channel lengths are not available. Various techniques are used to compensate for these shortcomings.
SRAM cells may be operated at a nominal supply voltage, even when surrounding logic is scaled to a lower supply voltage. However, this approach may require two separate voltage rails, which not only requires a more complicated power grid on the IC to ensure reliable power delivery, hut also introduces additional complexity when the signals cross different voltage domains within the IC. Redundancy and error-correction codes (ECC) may be used to detect and repair erroneous bits when SRAM cells fail. However, redundancy techniques increase the number of cells required to store a fixed amount of data and can also increase costs during testing or add latency to memory access operations. Peripheral assist circuits can be utilized to alter internal voltages in the SRAM cells during memory access operations, but again, this technique adds additional complexity and increases the energy consumption of the memory array. Finally, larger device sizes and/or larger timing margins may be used in the design of critical circuits to ensure correct operation, but this solution is not an efficient use of die space. Thus, there is a need for addressing these issues and/or other issues associated with the prior art.